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slws092g ? july 2000 ? revised february 2005 1 post office box 655303 ? dallas, texas 75265 single-chip rf transmitter for 868-mhz and 915-mhz ism bands 850-mhz to 950-mhz operation fm/fsk operation for transmit 24-bit direct digital synthesizer (dds) with 11-bit dac on-chip voltage-controlled oscillator (vco) and phase-locked loop (pll) on-chip reference oscillator minimal external components required low power consumption typical output power of 7 dbm typical output frequency resolution of 230 hz ultrafast lock times from dds implementation two fully-programmable operational modes 2.2-v to 3.6-v operation flexible serial interface to ti msp430 microcontroller 24-pin plastic thin-shrink small-outline package (tssop) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pw package (top view) pd_out1 pll_vcc pd_set vco_tank1 vco_tank2 pll_gnd dig_gnd clock data strobe mode stdby pd_out2 lockdet pa_out pa_gnd pa_vcc gnd dig_vcc xosc2 xosc1 dig_gnd tx_data nc description the trf4900 single-chip solution is an integrated circuit intended for use as a low cost fsk transmitter to establish a frequency-agile rf link. the device is available in a 24-lead tssop package and is designed to provide a fully-functional multichannel transmitter. the chip is intended for linear (fm) or digital (fsk) modulated applications in the new 868-mhz european band and the north american 915-mhz ism band. the single chip transmitter operates down to 2.2 v and is expressly designed for low power consumption. the synthesizer has a typical channel spacing of approximately 230 hz to allow narrow-band as well as wide-band applications. due to the narrow channel spacing of the direct digital synthesizer (dds), the dds can be used to adjust the tx frequency and allows the use of inexpensive reference crystals. two fully-programmable operation modes, mode0 and mode1, allow extremely fast switching between two preprogrammed settings (e.g., tx_frequency_0/tx_frequency_1) without reprogramming the device. each functional block of the transmitter can be specifically enabled or disabled via the serial interface. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foa m during storage or handling to prevent electrostatic damage to the mos gates. copyright ? 2005, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
slws092g ? july 2000 ? revised february 2005 2 post office box 655303 ? dallas, texas 75265 ism band standards europe has assigned a new unlicensed frequency band of 868 mhz to 870 mhz. this new band is specifically defined for short range devices with duty cycles from 0.1% to 100% in several sub-bands. the existing 433-mhz band for short-range devices in europe has the great disadvantage of very high usage. the new european frequency band, due to the duty cycle assignment, allows a reliable rf link and makes many new applications possible. the north american unlicensed ism (industrial, scientific, and medical) band covers 902 mhz to 928 mhz (center frequency of 915 mhz) and is suitable for short range rf links. transmitter the transmitter consists of an integrated vco, a complete fully-programmable direct digital synthesizer, and a power amplifier. the internal vco can be used with an external tank circuit or an external vco. the divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete dds with a typical frequency resolution of 230 hz. the 8-bit fsk frequency deviation register determines the frequency deviation in fsk mode. the modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. since the typical rf output power is approximately 7 dbm, no additional external rf power amplifier is necessary in most applications. the trf4900 rf transmitter is suitable for use in applications that include the trf6900 rf transceiver. baseband interface the trf4900 can easily be interfaced to a baseband processor such as the texas instruments msp430 ultralow-power microcontroller (see figure 1). the trf4900 serial control registers are programmed by the msp430 and the msp430 performs baseband operations in software. transmit data lock detect mode select serial control data serial control clock serial control strobe tx_data lockdet mode stdby data clock strobe pa_out trf4900 transmitter + discretes rf section programmable digital i/o pins msp430 family c microcontroller section antenna standby rf out figure 1. system block diagram for interfacing to the msp430 microcontroller
slws092g ? july 2000 ? revised february 2005 3 post office box 655303 ? dallas, texas 75265 functional block diagram vco direct digital synthesizer, power-down logic, and buffers strobe data clock pll xosc1 trf4900 8 9 10 16 17 serial interface power amplifier pll_vcc pd_out2 pd_out1 1 2 3 4 5 6 7 18 19 20 21 22 23 24 vco_tank1 vco_tank2 pll_gnd dig_gnd xosc2 dig_vcc gnd pa_vcc pa_gnd pa_out lockdet mode 11 stdby 12 dig_gnd 15 tx_data 14 nc 13 pd_set
slws092g ? july 2000 ? revised february 2005 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description clock 8 i serial interface clock signal data 9 i serial interface data signal dig_gnd 7, 15 digital ground dig_vcc 18 digital supply voltage gnd 19 ground lockdet 23 o pll lock detect output, active high. pll locked when lockdet = 1. mode 11 i mode select input. the functionality of the device in mode0 or mode1 can be programmed via the a-, b-, c-, and d-words of the serial control interface. nc 13 no connection pa_gnd 21 power amplifier ground pa_out 22 o power amplifier output, open collector pa_vcc 20 power amplifier supply voltage pd_out1 1 o charge pump output ? pll in locked condition pd_out2 24 o charge pump output ? pll in unlocked condition pd_set 3 charge pump current setting terminal. an external resistor, r pd , is connected to this terminal to set the nominal charge pump current. pll_gnd 6 pll ground pll_vcc 2 pll supply voltage stdby 12 i standby control for the trf4900, active low. while stdby = 0, the contents of the control registers are still valid and can be programmed via the serial control interface. strobe 10 i serial interface strobe signal tx_data 14 i digital modulation buffered input for fsk/fm modulation of the carrier, active high vco_tank1 4 i vco tank circuit connection. should be left open if an external vco is used. vco_tank2 5 i vco tank circuit connection. may also be used to input an external vco signal. xosc1 16 o reference crystal oscillator connection xosc2 17 i reference crystal oscillator connection. may be used as a single-ended clock input if an external crystal is not used.
slws092g ? july 2000 ? revised february 2005 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage range, pa_vcc, pll_vcc, dig_vcc, vcc (see note 1) ?0.6 to 4.5 vdc . . . . . . . . . . . . . . . . input voltage, logic signals ?0.6 to 4.5 vdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd integrity ? 2 kv hbm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ? rf terminal 22, pa_out, is not protected against voltage stress higher than 800 v hbm. note 1: all gnd and vcc terminals must be connected to either ground or supply, respectively, even if the function block is not used. recommended operating conditions min typ max unit supply voltage, pa_vcc, pll_vcc, dig_vcc, dds_vcc, vcc 2.2 3.6 v operating temperature ?20 60 c high-level input voltage, v ih (data, clock, strobe, tx_data, mode, stdby ) v cc ?0.5 v low-level input voltage, v il (data, clock, strobe, tx_data, mode, stdby ) 0.5 v high-level output voltage, v oh (lockdet); i oh = 0.5 ma v cc ?0.5 v low-level output voltage, v ol (lockdet); i ol = 0.5 ma 0.5 v electrical characteristics over full range of operating conditions, (typical values are at pa_vcc, pll_vcc, dig_vcc, vcc = 3 v , t a = 25 c) (unless otherwise noted) supply current consumption in each mode mode active stages min typ max unit power down (standby mode) none 0.5 a pa state 0-db attenuation 58 75 tx 10-db attenuation dds, pll, vco, pa 27 ma tx 20-db attenuation dds, pll, vco, pa 22 ma pa disabled 10 12.5 vco parameter test conditions min typ max unit frequency range 850 950 mhz phase noise 50-khz offset ?94 dbc/hz tuning voltage 0.5 v cc ? 0.4 v
slws092g ? july 2000 ? revised february 2005 6 post office box 655303 ? dallas, texas 75265 electrical characteristics over full range of operating conditions, (typical values are at pa_vcc, pll_vcc, dig_vcc, vcc = 3 v , t a = 25 c) (unless otherwise noted) (continued) direct digital synthesizer (dds) parameter test conditions min typ max unit reference oscillator input frequency, ? ref as oscillator 15 26 mhz reference oscillator input frequency, ? ref as buffer 15 26 mhz programmable dds divider ratio 22 bits 0 4194303 dds divider resolution, ?? n ? ref 2 24 fsk ? modulation register ratio 8 bits 0 1020 fsk ? modulation resolution n ? ref 2 22 pll parameter test conditions min typ max unit rf input frequency 850 950 mhz rf input power internal vco bypassed; external input applied to vco_tank2 ?10 dbm rf input divider ratio, n 256 512 rf output frequency resolution n ? ref 2 24 charge pump current programmable with external resistor, 100 k ? nominal, apll = 0 70 a power amplifier parameter test conditions min typ max unit frequency range 850 950 mhz 0-db attenuation 7 amplifier output power (see note 2) 10-db attenuation ?3 dbm amplifier output power (see note 2) 20-db attenuation ?12 dbm amplifier off ?52 optimal load impedance see figure 11 ? 2 nd -order harmonic v cc = 3 v, 0-db attenuation ?13 dbc 3 rd -order harmonic v cc = 3 v, 0-db attenuation ?32 dbc note 2: the device and output matching network (see application information section) is designed to provide the output power into a 50- ? load. the device stability was tested (no parasitic oscillations) with an output vswr of 10:1 over all phase angles and is not tested in production. typical mode switching and lock times operation test conditions min typ max unit standby to transmit time ? from rising edge of stdby to valid rf signal at p a_out, apll = 111b (maximum) 500 s ? highly dependent upon loop filter topology
slws092g ? july 2000 ? revised february 2005 7 post office box 655303 ? dallas, texas 75265 timing data for serial interface (see figure 2) parameter min max unit f (clock) clock frequency 20 mhz t w(clkhi) clock high time pulse width, clock high 25 ns t w(clklo) clock low time pulse width, clock low 25 ns t su(data) setup time, data valid before clock high 25 ns t h(data) hold time, data valid after clock high 25 ns t w(strobehi) strobe high time pulse width, strobe high (see note 3) 25 ns t w(strobelo) strobe low time pulse width, strobe low 25 ns note 3: clock and data must both be low when strobe is asserted (strobe = 1). t w(clkhi) clock data strobe t su(data) t h(data) t w(strobehi) t w(strobelo) t w(clklo) figure 2. serial data interface timing detailed description reference oscillator the reference oscillator provides the dds system clock. it allows operation, with a suitable external crystal, between 15 mhz and 26 mhz. an external oscillator can be used to supply clock frequencies between 15 mhz and 26 mhz. the external oscillator should be directly connected to xosc2, terminal 17. the other oscillator terminal (xosc1, terminal 16) should be left open or can be used as a buffered version of the signal applied at terminal 17 (see figure 3). the same crystal or externally supplied oscillator signal is used to derive both the transmit and receive frequencies. 17 16 external signal, ? ref nc xosc1 xosc2 figure 3. applying an external oscillator signal
slws092g ? july 2000 ? revised february 2005 8 post office box 655303 ? dallas, texas 75265 detailed description (continued) direct digital synthesizer general principles of dds operation in general, a direct digital synthesizer (dds) is based on the principle of generating a sinewave signal in the digital domain. benefits include high precision, wide frequency range, a high degree of software programmability, and extremely fast lock times. figure 4 shows a block diagram of a typical dds. it generally consists of an accumulator, sine lookup table, a digital-to-analog converter, and a low-pass filter. all digital blocks are clocked by the reference oscillator. synthesizer frequency register n-bit register + sine lookup table dac low-pass filter analog output signal load with frequency word figure 4. typical dds block diagram the dds constructs an analog sine waveform using an n-bit adder counting up from 0 to 2 n in steps of the frequency register whereby generating a digital ramp waveform. each number in the n-bit output register is used to select the corresponding sine wave value out of the sine lookup table. after the digital-to-analog conversion, a low-pass filter is necessary to suppress unwanted spurious responses. the analog output signal can be used as a reference input signal for a phase-locked loop (pll). the pll circuit multiplies the reference frequency by a predefined factor. trf4900 direct digital synthesizer implementation figure 5 shows a block diagram of the dds implemented in the trf4900. it consists of a 24-bit accumulator clocked by the reference oscillator along with control logic settings. dds mode0 frequency setting mode0/1 select logic 24-bit register dds frequency register modulation control logic 22 22 24 8 + + 24 11 11-bit dac sine shaper low-pass filter tx_data ? (terminal 14) c ? word / mm bit (modulation mode select) ? dds to pll fsk frequency deviation register d ? word / dev bits (fsk deviation) a ? word mode ? (terminal 11) b ? word dds mode1 frequency setting reference frequency, ? ref figure 5. dds block diagram as implemented in the trf4900
slws092g ? july 2000 ? revised february 2005 9 post office box 655303 ? dallas, texas 75265 trf4900 direct digital synthesizer implementation (continued) the frequency of the reference oscillator, ? ref , is the dds sample frequency, which also determines the maximum dds output frequency. together with the accumulator width (in bits), the frequency resolution of the dds can be calculated. multiplied by the divider ratio (prescaler) of the pll, n, the minimum frequency step size of the trf4900 is calculated as follows: ? n ? ref 2 24 the 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the a-word determines the mode0 frequency, the b-word determines the mode1 frequency) with the two msb bits set to 0. consequently, the maximum bit weight of the dds system is reduced to 1/8 (see figure 6). this bit weight corresponds to a vco output frequency of ( ? ref /8) n. depending on the mode terminal?s (terminal 11) logic level, the internal mode select logic loads the frequency register with either the dds_0 or dds_1 frequency (see figure 5 and figure 6). dds frequency setting for mode0/1 from a-word/b-word 22 0 0 x x . . . . . . . xx xxx msb lsb 23 22 21 20 . . . . . . 4 3 2 1 0 msb 23 22 dds frequency register 8 fsk frequency deviation register ? dev 00 . . . . x00 xxxxxxx lsb 9 8 7 6 5 4 3 2 1 0 . . . . dds frequency register . . . . . . . . bit weight: 1/2 1/4 1/8 1/16 . . . . . . 1 2 24 figure 6. implementation of the dds frequency and fsk frequency deviation in the dds frequency register the vco output frequency, ? out , which is dependent on the dds_x frequency settings (dds_0 in the a-word or dds_1 in the b-word), can be calculated as follows: ? out dds_x n ? ref 2 24 n ? ref dds_x 2 24 if fsk modulation is selected (mm=0; c-word, bit 16), then the 8-bit fsk deviation register can be used to program the frequency deviation of the 2-fsk modulation. figure 6 illustrates where the 8 bits of the fsk deviation register map into the 24-bit dds frequency register. since the two lsbs are set to 0, the total fsk deviation can be determined as follows: ? 2?fsk n dev ? ref 2 22 hence, the 2-fsk frequency, set by the level on the tx_data is calculated as follows: ? out1:tx_data low n ? ref dds_x 2 24 ? out2:tx_data high n ? ref ( dds_x 4 dev ) 2 24 this frequency modulated output signal is used as a reference input signal for the pll circuit. channel width (frequency deviation) for 2-fsk modulation and channel spacing are software programmable. the minimum channel width and minimum channel spacing depend on the rf system frequency plan.
slws092g ? july 2000 ? revised february 2005 10 post office box 655303 ? dallas, texas 75265 trf4900 direct digital synthesizer implementation (continued) note that the frequencies ? out1 and ? out2 are centered about the frequency ? center = ( ? out1 + ? out2 )/2. when transmitting fsk, ? center is considered to be the effective carrier frequency and any receiver local oscillator (lo) should be set to the same ? center frequency the receiver?s if frequency ( ? if ) for proper reception and demodulation. for the case of low-side injection, the receiver lo would be set to ? lo = ? center ? ? if . conversely, for high-side injection, the receiver lo would be set to ? lo = ? center + ? if . since the dds registers are static, preprogrammed values are retained during standby mode. this feature greatly reduces turnon time, reduces current consumption when coming out of standby mode, and enables fast lock-times. the pll lock-times ultimately determine when data can be transmitted or received. phase-locked loop the phase-locked loop (pll) of the trf4900 consists of a phase detector (pd) and a frequency acquisiton aid (fd) (including two charge pumps), an external loop filter, voltage-controlled oscillator (vco), and a programmable fixed prescaler (n-divider) in the feedback loop (see figure 7). the pll as implemented in the trf4900 multiplies the dds output frequency and further suppresses the unwanted spurious signals produced by the direct digital synthesizer. external loop filter vco n-divider 256 / 512 ? dds i pd_1 i pd_2 ? out pd fd 4, 5 1 24 dds ? ref figure 7. basic pll structure vco a modified colpitts oscillator architecture with an external resonant circuit is used for the trf4900. the internal bias current network adjusts the signal amplitude of the vco. this allows a wide range of q-factors (30 60) for the external tank circuit. the vco can be bypassed by applying an external rf signal at vco_tank2, terminal 5. to drive the internal pll and power amplifier, a typical level of ?10 dbm should be applied. when an external vco is used, the x_vco bit should be set to 0. phase detector and charge pumps the trf4900 contains two charge pumps for locking to the desired frequency: one for coarse tuning of the frequency differences (called the frequency acquisition aid) and one for fine tuning of the phase differences (used in conjunction with the phase detector). the xor phase detector and charge pumps produce a mean output current that is proportional to the phase difference between the reference frequency and the vco frequency divided by n; n = 256 or 512. the trf4900 generates the current pulses i pd_1 during normal operation (pll locked). an additional slip detector and acquisition aid charge pump generates current pulses at terminal pd_out2 during the lock-in of the pll. this charge pump is turned off when the pll locks in order to reduce current consumption. the multiplication factor of the acquisition aid current i pd_2 can be programmed by three bits (apll) in the c-word.
slws092g ? july 2000 ? revised february 2005 11 post office box 655303 ? dallas, texas 75265 phase detector and charge pumps (continued) the slip detector output, pd_out2, at terminal 24 should be connected directly to the loop filter capacitor c 1 , as shown in figure 10. the nominal charge pump current i 0 is determined by the external resistor r pd , connected to terminal 3, and can be calculated as follows: i 0 7v r pd during normal operation (pll locked), the acquisition aid charge pump is disabled and the maximum charge pump current i pd_1 is determined by the nominal value i 0 (see figure 8). i pd_1 1 i 0 figure 8. normal operation charge pump current, i pd_1 each time the pll is in an unlocked condition, the acquisition aid charge pump generates current pulses i pd_2 . the i pd_2 current pulses are apll times larger than i 0 (see figure 9). i pd_1 1 i 0 i pd_2 apll figure 9. acquisition aid, i pd_2 , and normal operation, i pd_1 , charge pump currents programmable divider the internal divider ratio, n, can be set to 256 or 512 via the c-word. since a higher divider ratio adds additional noise within the multiplication loop, the lowest divider ratio possible for the target application should be used. loop filter loop filter designs are a balance between lock-time, noise, and spurious suppression. for the trf4900, common loop filter design rules can be used to determine an appropriate low-pass filter . standard formulas can be used as a first approach to calculate a basic loop filter. figure 10 illustrates a basic 3 rd -order loop filter. vco_tank1 vco_tank2 4 l 1 c 3 c 3c c 3d r 2 c 2 c 1 r 1 24 1 pd_out1 pd_out2 c 4 2nd-order loop filter 5 vco 3rd-order loop filter figure 10. basic 3 rd -order loop filter structure
slws092g ? july 2000 ? revised february 2005 12 post office box 655303 ? dallas, texas 75265 loop filter (continued) for maximum suppression of the unwanted frequency components, the loop filter bandwidth should generally be made as narrow as possible. at the same time, the filter bandwidth has to be wide enough to allow for the 2-fsk modulation and appropriate lock-time. a detailed simulation of the phase-locked loop should be performed and later verified on pcb implementations. power amplifier the power amplifier (pa) can be programmed via two bits (p0 and p1 in the d-word) to provide varying output power levels. several control loops are implemented internally to set the output power and to minimize the sensitivity of the power amplifier to temperature, load impedance, and power supply variations. the output stage of the pa usually operates in class-c and enables easy impedance matching. p a_out, terminal 22, is an open collector output terminal. 2 ?2 2 ?0.5 0.5 1 1 1 u 5 1 0.5 0.2 0 ?1 ?5 start 850 mhz stop 950 mhz ch1 s22 cal ofs cpl fil 1k 10 figure 11. power amplifier output impedance (s22) at device terminal 22
slws092g ? july 2000 ? revised february 2005 13 post office box 655303 ? dallas, texas 75265 principles of operation serial control interface a 3-wire unidirectional serial bus (clock, data, strobe) is used to program the trf4900 (see figure 12). the internal registers contain all user programmable variables including the dds frequency setting registers, as well as all control registers. at each rising edge of the clock signal, the logic value on the data terminal is written into a 24-bit shift register. setting the strobe terminal high loads the programmed information into the selected latch. while the strobe signal is high, the data and clock lines must be low (see figure 2). since the clock and strobe signals are asynchronous, care should be taken to ensure the signals remain free of glitches and noise. as additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. due to the static cmos design, the serial interface consumes virtually no current and it can be programmed in active as well as in standby mode. clock strobe data serial interface logic addr addr decoder shift register 3 a - latch b - latch c - latch d - latch 22 22 21 21 e - latch 21 figure 12. serial interface block diagram the control words are 24 bits in length. the first incoming bit functions as the most significant bit (msb). to fully program the trf4900, four 24-bit words must be sent: the a-, b-, c-, and d-words. if individual bits within a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. figure 13 shows the definition of the control words. t ables 1, 2, and 3 describe the function of each parameter. the e-latch, addressed by an addr equal to 111, is reserved for test purposes and should not be used. inadvertently addressing the e-latch activates the test modes of the trf4900. if the test mode has been inadvertently activated, it can only be exited by switching v cc on and off or by clearing the e-latch. the e-latch can be cleared by addressing it and resetting its entire contents by programming 1110 0000 0000 0000 0000 0000. as part of a proper power-up sequence, it is recommended to clear the e-latch each time v cc is applied before starting further operations with the trf4900.
slws092g ? july 2000 ? revised february 2005 14 post office box 655303 ? dallas, texas 75265 principles of operation mm apll 23 0 addr a-word (programming of dds_0) c-word (control register for pll, data slicer, and mode1 settings) pll xx mode1 control register [12?9] npll pa d-word (control register for modulation and mode0 settings) modulation register [20?13] dev lsb msb a2 a1 a0 p1 p0 b-word (programming of dds_1) lsb msb lsb msb addr lsb msb mode0 control register [12?9] addr 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 23 0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 101 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 110 pll pa p1 p0 dds frequency setting for mode0 (dds_0 [21?0]) dds frequency setting for mode1 (dds_1 [21?0]) dv7 dv6 dv5 dv4 dv3 dv2 dv1 dv0 x x x x x x x x x x x x x x x x x x x addr vco pll vco note: start programming with msb and ensure that the clock and data lines are low during the rising edge of the strobe signal. figure 13. serial control word format
slws092g ? july 2000 ? revised february 2005 15 post office box 655303 ? dallas, texas 75265 principles of operation table 1. mode0 control register description (d-word) symbol bit number description initial settings after power up symbol bit location number of bits description default state default value 0_pa [10?9] power amplifier mode disabled 00b 2 p1 p0 0 0 = disabled 0 1 = 10-db attenuation, enable modulation via tx_data 1 0 = 20-db attenuation, enable modulation via tx_data 1 1 = 0-db attenuation, enable modulation via tx_data 0_vco [11] 1 during operation, this bit should always be enabled (1 = enabled), unless an external vco is used. disabled 0b 0_pll [12] 1 enable pll (dds system, vco, rf divider, phase comparator and charge pump) 1 = enabled 0 = disabled disabled 0b table 2. mode1 control register description (c-word) symbol bit number description initial settings after power up symbol bit location number of bits description default state default value 1_pa [10?9] power amplifier mode disabled 00b 2 p1 p0 0 0 = disabled 0 1 = 10-db attenuation, enable modulation via tx_data 1 0 = 20-db attenuation, enable modulation via tx_data 1 1 = 0-db attenuation, enable modulation via tx_data 1_vco [11] 1 during operation, this bit should always be enabled (1 = enabled), unless an external vco is used. disabled 0b 1_pll [12] 1 enable pll (dds system, vco, rf divider, phase comparator and charge pump) 1 = enabled 0 = disabled disabled 0b
slws092g ? july 2000 ? revised february 2005 16 post office box 655303 ? dallas, texas 75265 principles of operation table 3. miscellaneous control register description symbol word bit number description initial settings after power up symbol word bit location number of bits description default state default value dds_0 a-word [21?0] 22 dds frequency setting in mode0 0 all 0s dds_1 b-word [21?0] 22 dds frequency setting in mode1 0 all 0s dev d-word [20?13] 8 fsk frequency deviation register 0 all 0s apll c-word [20?18] 3 acceleration factor for the frequency acquisition aid charge pump a2 a1 a0 0 0 0= 1 0 0 1= 20 0 1 0= 40 0 1 1= 60 1 1 1= 140 0 000b npll c-word [17] 1 pll divider ratio 0 = divide by 256 1 = divide by 512 256 0b mm c-word [16] 1 modulation mode select. sets the behavior of terminal tx_data to fsk data input. 0 = fsk/fm 1 = do not use fsk mode 0b operating modes table 4 and table 5 illustrate operating modes and transmit frequencies as set by the stdby , mode, and tx_data terminals used in conjunction with the dds frequency settings. table 4. transmitting data in fsk mode (mm bit set to 0) terminal transmit frequency stdby mode tx_data transmit frequency 1 0 0 ? out = ? ref n (dds_0)/2 24 1 0 1 ? out = ? ref n (dds_0 + 4 dev)/2 24 1 1 0 ? out = ? ref n (dds_1)/2 24 1 1 1 ? out = ? ref n (dds_1 + 4 dev)/2 24
slws092g ? july 2000 ? revised february 2005 17 post office box 655303 ? dallas, texas 75265 principles of operation operating modes (continued) table 5. operating mode per stdby terminal stdby operating mode 0 standby/programming mode ? power down of all blocks 1 operating mode and programming mode two independent operating modes, mode0 and mode1, allow extremely fast switching between two preprogrammed settings by toggling the mode terminal. each mode can be viewed as a bank of configuration registers which store the frequency settings and the enable/disable settings for each functional block of the trf4900. the mode terminal is then used to asynchronously switch between mode0 and mode1 as shown in figure 14. table 6 shows several examples of operating sequences. power amplifier mode vco enable pll enable synthesizer: mode0 register settings (d-word) power amplifier mode vco enable pll enable synthesizer: mode1 register settings (c-word) mode terminal (terminal 11) = 1 mode terminal (terminal 11) = 0 dds frequency dds frequency figure 14. interaction between mode terminal and preprogrammed mode0 and mode1 control registers table 6. operating mode examples function / description mode0 mode1 transmit on two different frequencies transmit on frequency 0 transmit on frequency 1 emulate fsk transmit operation using the mode terminal for wideband fsk transmit on frequency 0 transmit on frequency 0 + deviation
slws092g ? july 2000 ? revised february 2005 18 post office box 655303 ? dallas, texas 75265 application information a typical application schematic for an fsk system operating in the european 868-mhz to 870-mhz ism band is shown in figure 15. if the trf4900 is left on for long periods of time without going into standby mode, a 100- ? resistor to ground should be added at terminal 4 or terminal 5 to reduce tuning voltage drift as in figure 16. if the 100- ? resistor is present, c2 and c4 may be changed to adjust the tuning range as needed. since most eu applications involve relatively short periods of transmission, the 100- ? resistor is left off in the schematic shown in figure 15. vco direct digital synthesizer and power-down logic pll trf4900 clock data strobe 16 17 serial interface power amplifier 1 2 3 4 5 6 7 18 19 20 21 22 23 24 mode stdby 15 14 13 8 9 10 11 12 2.7 pf c4 l8 10 nh 5.6 pf c2 v1 smv1233?011 c17 r1 10 k ? 8.2 k ? r4 c32 820 pf c1 8.2 nf l1 5.6 nh c5 150 pf nc c14 3.3 p f j1 rf_out sma/b/l tx_data lockdet c25 15 pf 1 m ? r6 c24 15 pf r5 820 ? 18 mhz cq1 68 k ? r3 c3 150 pf r2 51 ? 150 pf figure 15. typical application schematic for 868-mhz to 870-mhz european ism band
slws092g ? july 2000 ? revised february 2005 19 post office box 655303 ? dallas, texas 75265 application information external component list for figure 15 (5% tolerance unless otherwise noted) designator description (size) value manufacturer part number/comments c1 capacitor 8.2 pf c2 capacitor 5.6 pf c3 capacitor 150 pf c4 capacitor 2.7 pf c5 capacitor 150 pf c14 capacitor 3.3 pf c17 capacitor 150 pf c24 capacitor 15 pf c25 capacitor 15 pf c32 capacitor 820 pf l1 coil 5.6 nh murata lqn21a6n8d04 l8 coil 10 nh murata lqw1608 r1 resistor 10 k ? r2 resistor 51 ? r3 resistor 68 k ? r4 resistor 8.2 k ? r5 resistor 820 ? r6 resistor 1 m ? v1 varactor diode smv1233-011 alpha industries cq1 crystal 18 mhz cmac frequency products cx-1 smi
slws092g ? july 2000 ? revised february 2005 20 post office box 655303 ? dallas, texas 75265 application information a typical application schematic for an fsk system operating in the north american 902-mhz to 928-mhz ism band as shown in figure 16. vco direct digital synthesizer and power-down logic pll trf4900 clock data strobe 16 17 serial interface power amplifier 1 2 3 4 5 6 7 18 19 20 21 22 23 24 mode stdby 15 14 13 8 9 10 11 12 3.9 pf c4 l8 10 nh 3.9 pf c2 v1 smv1247?079 10 k ? 27 k ? r4 c32 120 pf c1 820 pf c5 0.1 f nc c14 3.3 p f j1 rf_out sma/b/l tx_data lockdet c25 27 pf 1 m r6 c24 27 pf r5 100 ? 25.6 mhz or 26 mhz cq1 300 k ? r3 c26 sat dnp v2 smv1247?079 r7 10 k ? r1 r9 15 ? c34 0.1 f r2 51 ? l1 6.8 nh c6 0.1 f r8 100 k ? figure 16. typical application schematic for 902-mhz to 928-mhz north american ism band
slws092g ? july 2000 ? revised february 2005 21 post office box 655303 ? dallas, texas 75265 application information external component list for figure 16 (5% tolerance unless otherwise noted) designator description (size) value manufacturer part number/comments c1 capacitor 820 pf c2 capacitor 3.9 pf c4 capacitor 3.9 pf c5 capacitor 0.1 f c6 capacitor 0.1 f c14 capacitor 3.3 pf c24 capacitor 27 pf c25 capacitor 27 pf c26 capacitor select at test (sat), do not place (dnp) c32 capacitor 120 pf c34 capacitor 0.1 f l1 coil 6.8 nh murata lqn21a6n8d04 l8 coil 10 nh murata lqw1608 r1 resistor 10 k ? r2 resistor 51 ? r3 resistor 300 k ? r4 resistor 27 k ? r5 resistor 100 ? r6 resistor 1 m ? r7 resistor 10 k ? r8 resistor 100 k ? r9 resistor 15 ? v1, v2 varactor diode smv1247-079 alpha industries cq1 crystal 25.6 mhz or 26 mhz icm (international crystal manufacturing, incorporated) 865842: 25.6 mhz 865850: 26 mhz
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) trf4900pw nrnd tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TRF4900PWG4 nrnd tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year trf4900pwr nrnd tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year trf4900pwrg4 nrnd tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-aug-2008 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant trf4900pwr tssop pw 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) trf4900pwr tssop pw 24 2000 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
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